Overview
Welcome to ECE 510 Fall 2024: 16nm FinFET IoT SoC Design and Fabrication!
The latest version of the syllabus can be found here: ECE510 Syllabus
Links to online resources
We will make extensive use of online resources below. Access to most is granted after you have signed the NDA with Intel.
- Course website: web.pdx.edu/~dburnett/tapeout (this page)
- Access granted after NDA processed:
- Course Slack instance: pdxtapeoutclass.slack.com
- #tapeout on psuece.slack.com has been deprecated -- only used for summer
- Intel Sharepoint: link in your email
- Course compute server: westcad.ece.pdx.edu
- GitLab instance ("gitlab.local") accessible by launching Firefox from a VNC session on compute server
- Google Drive shared drive called "tapeoutclass"
- Course Slack instance: pdxtapeoutclass.slack.com
- Course mailing list (announcements only): ece-tapeout-group@pdx
- Canvas will be used for posting grades only: https://canvas.pdx.edu/courses/93184
Other useful resources
- Chisel book: free to download at https://github.com/schoeberl/chisel-book
- Other tapeout classes' websites with more valuable information:
- Relevant SoC papers:
- Maksimovic et al, “A Crystal-Free Single-Chip Micro Mote with Integrated 802.15.4 Compatible Transceiver, sub-mW BLE Compatible Beacon Transmitter, and Cortex M0” VLSI’19
- D. Lovell et al., “SCμM-V23: Towards A Crystal-Free System-On-Chip For IoT In 16nm,” in 2024 IEEE Workshop on Crystal-Free/-Less Radio and System-Based Research for IoT (CrystalFreeIoT), May 2024, pp. 18–23. doi: 10.1109/CrystalFreeIoT62484.2024.00008.
- J. Myers, A. Savanth, R. Gaddh, D. Howard, P. Prabhat, and D. Flynn, “A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator,” IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 31–44, Jan. 2016, doi: 10.1109/JSSC.2015.2477046.
- P. Prabhat et al., “27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), Feb. 2020, pp. 422–424. doi: 10.1109/ISSCC19947.2020.9063136.
- M. Fojtik et al., “A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells,” IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp. 801–813, Mar. 2013, doi: 10.1109/JSSC.2012.2233352.
- Chen et al, “A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets” JSSC’21
- Tamura et al, “A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets” JSSC 12/20 Thijssen, et al, “A 370μW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver with >63dB Adjacent Channel Rejection at >2 Channels Offset in 22nm FDSOI” ISSCC’20
- Kim, et al, “A 1.04 - 4V, Digital-Intensive Dual-Mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with extended range in 28nm CMOS” RFIC’19
- Koninejburg et al, “A 769μW Battery-Powered Single-Chip SoC with BLE for Multi-Modal Vital Sign Health Patches” ISSCC’19
Week 1 Checklist
Make sure you have completed the following steps by the end of Week 1, or as soon as possible thereafter:
- Signed paper NDA w/ Dr. Burnett
- Signed Intel DocuSign
- Received access to PDXIntel16
- Submitted Pre-lab 1 and 2 results to “Tapeout Class Pre-lab Sign-off”
- Completed “Tapeout Class Interest Form F2024”
- Completed “SoC Skills Survey: Start of Term”
- Created gitlab.local account on westcad (verifies access to westcad)
- Signed up for a team in the team spreadsheet (verifies access to tapeoutclass shared drive)
- Verify access to pdxtapeoutclass Slack workspace
- Created an introduction slide
- Helped complete a team slide for your team
Preparation and Prerequisites
At the start of summer, emails went out to the department soliciting interest in the course. Students who completed the interest survey were added to a mailing list and a Slack channe, to communicate information and answer questions about pre-requisite labs.
By the start of the quarter all students need to have completed Pre-labs 1 and 2. These are vital to make sure we can we all have access to, and familiarity with, the software tools we will be using to produce our design.
Successful completion of the labs demonstrates readiness to undertake this special course. After completion, students will be asked to make an appointment with Dr. Burnett to sign the Intel NDA.
Pre-lab 1
Summary of emails sent to ece-tapeout-group regarding Pre-lab 1:
The first digital pre-lab is here: https://gitlab.cecs.pdx.edu/west/creating-a-gds/-/blob/main/chipyard_asap7_commercial.md
For me to give you access to the pre-lab link ("Developer" access permissions appear to be necessary), it looks like you must have logged in to MCECS GitLab at least once. If you are having access issues please log in once and then send me your GitLab username. To test your access, please also see if you can view this placeholder project: https://gitlab.cecs.pdx.edu/tapeout/test-project
For background, this will walk you though the full automated GDS generation flow using the copy of the ASAP7 7nm Academic PDK residing on MCECS servers. While we have tested this extensively, there will undoubtedly be bugs you will encounter. There will certainly be clarifications we should add. Feel free to suggest revisions or, ideally, submit a pull request through GitLab so we can review and integrate your suggested changes in a centralized place.
I encourage you all to get started on this as soon as you can so we can solve simple starting issues like permissions access or basic UNIX system troubleshooting. Asking questions in the Slack channel is preferred.
Be sure to fill out the Tapeout Class Interest Form if you have not done so already: https://forms.gle/qxddQhodRcyVhWjj9
Pre-lab 2
Summary of emails sent to ece-tapeout-group regarding Pre-lab 2:
Hi all, I'm happy to share the second pre-lab, attached as a PDF. This will take you through customization of what you did in Pre-lab 1 by first adding Chisel components, then adding custom Verilog components. Successfully completing this exercise is critical because we want to create new digital cores and attach them to the core processor and bus fabric. We intend to add the document to the gitlab repository in Markdown later but this format makes it available sooner.
This will be the last required pre-lab before the term starts. We also want to demonstrate adding custom analog IP layout to the digital synthesis flow, but that exercise will only be necessary for the folks undertaking RF, analog, or mixed-signal designs.
Pre-lab check-off
The first assignment, verifying Pre-labs 1 and 2 are completed, is due by the first lecture. This assignment also helps organize students into teams by getting them thinking about what they want their part of the class project to look like. Description:
"So we can stay on track with the course timeline, Pre-labs 1 and 2 must be completed by the start of the first lecture on Tuesday. Use this form to submit your results:
(If you are reading this after Lecture 1 because you enrolled in the course late, please let me know and complete Pre-labs 1 and 2 as soon as possible!)"
The deadline is approaching!
